1. Field of the Invention
Example embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor memory device storing data, for example, a DRAM device.
2. Description of the Related Art
Currently, data processing quantity and data processing speed of semiconductor memory devices have been increased, and in turn, semiconductor memory devices have attained higher capacitance and higher integration. However, further highly integrated semiconductor memory devices, e.g., DRAM devices, involve increased leakage current. An increase of the leakage current may decrease the reliability of a DRAM device, e.g., a refresh characteristic and a retention characteristic.
For example, increase of a refresh time and decrease of a retention time may dissipate an electric power of the DRAM device. Also, an Error Correction Code (ECC) circuit for a refresh control may occupy a large area to impede the increase of the integration of the DRAM device.
FIG. 1 is a circuit diagram of a conventional DRAM device.
Referring to FIG. 1, a DRAM device may include a transistor T and a capacitor C. The transistor T includes a gate G, a source S and a drain D. The capacitor C includes two electrodes E1 and E2. The drain D of the transistor T may be connected to a bit line BL, and the source S may be connected to one electrode E2 of the capacitor C. The gate G of the transistor T may be connected to a word line WL. The bit line BL may supply power and the word line WL may control the transistor T. Charge stored in the capacitor C may be gradually eliminated due to leakage current. For example, the leakage current may include a leakage current (first) occurring between the electrodes E1 and E2 of the capacitor C, an off-current (second) between the source S and the drain D of the transistor T, a junction leakage current (third) of the source S and the drain D of the transistor T, and a leakage current (fourth) of the gate G of the transistor T.
The first leakage current is related to the capacitor C, and the second through fourth leakage currents are related to the transistor T. Higher integration attained in the DRAM device is associated with a dimensional decrease of the transistor T. The decreased dimension of the transistor T may increase the foregoing second through fourth leakage currents. For example, the dimensional decrease of the transistor T may cause a length decrease of the gate G, a decrease of a junction depth of the source S and the drain D, a thickness decrease of a gate insulating layer (not shown) for insulating the gate G.
For example, a decrease of the gate length may cause a short channel effect to abruptly increase the off current of the transistor T. The decrease of the junction depth of the source S and the drain D may increase the junction leakage current. The decrease of the gate insulating layer may increase a Fowler-Nordheim (F-N) tunneling, increasing the leakage current of the gate G.
Therefore, in order to enhance the reliability of the highly integrated DRAM device, the leakage current must be decreased in the transistor portion.